Although it is a relatively new semiconductor technology, flash memory is well known and widely used in the art. Flash memory is nonvolatile, meaning that it retains its content even if power is removed. This is in contrast to volatile memory technologies like static random access memory ("SRAM") and dynamic random access memory ("DRAM") that require continuous power to store information. Flash memory's cell structure and erasable programmable read-only memory ("EPROM") foundation also insure that it is extremely cost-effective to manufacture, continually scalable to higher densities, and highly reliable. This is a combination of characteristics that other semiconductor memory technologies currently lack.
In contrast to EPROM's, however, which can only be erased through exposure to ultra violet light, the flash memory array is electrically erasable in bulk. This distinguishes it from traditional electrically erasable programmable read-only memory ("EEPROM") that are by definition byte-alterable. The flash memory erase function empties part of the device all at once. The device can be programmed (written to) incrementally, however, which is an important capability for applications that require data/file updates.
Flash memory can be read very quickly. However, it takes a significantly longer amount of time to write information into flash memory or to erase the flash memory than it does to read the memory. Part of the reason for this is that, while a location is simply read from flash memory, writing and erasing is an iterative process. Each erase or write operation must be repeated several times and verified to insure that the erasure or write operation has completed successfully. Normally, when neither the write nor erase operations are enabled, the flash memory unit is by default in a read state.
Address transition detection ("ATD") is also well known in the art and has been widely used in SRAM and EPROMs. The purpose of address transition detection circuitry is to increase the speed with which data can be read from memory. This is accomplished by performing operations which are required for every memory read operation as soon as an address transition has been detected.
These operations include equalizing sense amplifiers and latching the previous output. The sense amplifiers are used to increase weak signals sensed from the memory cells to be read during the read operation. Equalizing the sense amplifiers causes the amplifiers to be cleared or otherwise set up so that they are ready to process the new data to be read. Latching the previous output of the output to stay static until the new data from the read operation has been output from the sense amplifiers. The previous output is latched because the output of the sense amplifiers fluctuates before it finally reaches a steady value. Latching the previous output ensures that the swing does not pass down to the outputs.
Circuitry to equalize the sense amplifiers and latch pervious output is well known in the art. In fact, both operations are normally performed during a memory read operation. The address detection circuitry of the present invention simply permits these operations to be performed earlier than would be the case where address transition detection is not employed. However, noise on address lines can cause an ATD scheme to fail by beginning a read operation on an improper address.